1. Field of the Invention
This invention relates to circuitry for generating synchronized clock signals employed in data processing and transmission systems and, more particularly, to generating such clock signals on a decentralized basis for use in multi-chip microprogrammed processors.
2. Description of the Prior Art
In the control of individual processing steps, digital information processing systems require a plurality of control signals by means of which the individual processing elements such as, for example, registers and logic circuits, are activated in a fixed order. In accordance with state-of-the-art practice, these clock control signals are centrally generated in synchronous processing systems and distributed to the individual component groups. For this purpose, the clock control signals are generated from the periodic pulses of a clock by logically combining them with function control signals such as, for example, program instructions and system state indicators. To minimize distortions and time delay effects occurring when the clock control signals are distributed to the user elements, identical line lengths or lines having adjustable delays are used.
However, this type of clock control signal generation is less suitable for systems which employ modern, highly integrated circuit chips. The progress made in circuit technology permits an ever increasing number of functions to be integrated in a single chip, thereby considerably increasing the processing speed and the transfer speed from one logic stage to the next. Because of these enhanced capabilities, the clock frequency at which such circuits operate is very high.
The clock frequency usable when several chips are connected to form a system is substantially reduced as a result of the interconnections which are required, in such a case, between one circuit chip and the next. A decisive factor responsible for this is the delays of centrally generated control signals. The relatively great line lengths and the plurality of logic stages which each entrail different chip dependent delays, limit the clock frequency of the whole system as a function of the signal path having the longest delay. To illustrate this, attention is drawn to the fact that with modern chip technologies, typical delays between two logic stages on a chip amount to several nanoseconds, which the delay of the drivers alone for lines to adjacent chips is of the order of some ten nanoseconds.
A further essential aspect of such systems is the number of connecting points available for each chip, which are largely dependent on the size and the circumference of the circuit chip. If the logic capacity is to be effectively utilized at increased circuit density, the functions executed on a circuit chip have to be chosen in such a manner that the number of connecting points required are reduced to a minimum.
In producing complex systems from highly integrated circuit chips, it has already been proposed in prior art material to couple to each other several independently and asynchronously operating subsystems, each consisting of one circuit chip, see for example Deutsche Offenlegungsschrift No. 24 57 553. However, asynchronous operation necessitates extensive control unit management. If the circuit chips are interconnected by a common bus, for example, each new information exchange necessitates a request procedure for establishing connection. The time requirements this involves are often not tolerable in data processing system. The long and different delays of clock control signals are particularly detrimental in microprogrammed systems, limiting an increase of the system's operating frequency, which would otherwise be possible from the standpoint of circuit technology. During micro instruction processing, the delay resulting from the distribution of centrally generated clock control signals becomes increasingly intolerable, decisively limiting the speed. The principal factors previously responsible for this were the cycle time of the control storage and the delay of the logic stages.